Пермяков Валерий
Инженер по верификации FPGA - НПП ЦРТС
Saint Petersburg, Russia
Attended conferences (1)
Talks (1)
  • 23.07.2014
    Functional verification of HDL code

    This presentation covers the topic of digital circuit functional verification. A Hardware Description Language (HDL) is used to program the structure and operation of digital circuits. A brief introduction to digital circuit design and verification is given. The difference between hardware testing and verification is outlined. The main principles of HDL code functional verification are covered. Applicability of various techniques is discussed, as well as these methods' particular aspects of deployment.

    • Average
    • 40 min
    • SQA Days / 16
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